1. Field of the Invention
The present invention relates to a data latch circuit configured to latch a data signal using one clock signal selected from among multiple clock signals.
2. Description of the Related Art
A semiconductor test apparatus (which will be referred to simply as the “test apparatus” hereafter) is used to test whether or not a device under test operates normally. Such a test apparatus acquires the level of a data signal at each edge timing of a clock signal that is synchronized with the data signal so as to acquire the value of the data signal. The test apparatus judges whether or not the value of the data signal thus acquired matches an expected value so as to judge the quality of the device under test, or so as to identify defective parts.
There are various kinds of known signal formats used as an output signal of a semiconductor device. FIGS. 1A and 1B are diagrams each showing an example configuration of a test system.
A device under test (DUT) 1 shown in FIG. 1A outputs multiple data signals D1 and D2 and clock signals CLK1 and CLK2 that correspond to the multiple data signals D1 and D2 in a one-to-one manner. The data signals D1 and D2 are synchronized with the edges of the respective clock signals CLK1 and CLK2.
A test apparatus 2a includes multiple test pins P1 through P4 connected to device pins of a DUT1a in a one-to-one manner, and includes circuit blocks which will be referred to as the pin electronics circuits PE1 through PE4 which are respectively provided to the test pins P1 through P4. Each pin electronics circuit PE includes a driver configured to output a signal to the DUT 1 or a comparator configured to judge the level of the data signal received from the device under test.
With a test system shown in FIG. 1A, the pin electronics circuit PE1 connected to the first pin P1 latches the data signal D1 at an edge timing of the clock signal CLK1 input to the second pin P2. In the same way, the pin electronics circuit PE3 connected to the third pin P3 latches the data signal D2 at an edge timing of the clock signal CLK2 input to the fourth pin P4.
With a test system shown in FIG. 1B, a DUT1b outputs multiple data signals D11 and D12 and a their common clock signal CLK1. The data signals D11 and D12 are synchronized with an edge of the common clock signal CLK1. With such a system, the pin electronics circuit PE1 connected to the first pin latches the data signal D11 at an edge timing of the clock signal CLK1 input to the third pin P3. Furthermore, the pin electronics circuit PE2 circuit connected to the second pin latches the data signal D12 at an edge timing of the clock signal CLK1 input to the third pin P3.
Such a test apparatus is required to have the versatility to support various kinds of DUTs having various signal formats. For example, directing attention to the pin electronics circuit PE1 connected to the first pin P1, if the pin electronics circuit PE1 is capable of acquiring (latching) the data signal D1 (D11) input to the first pin P1 to which it is connected, according to a clock signal that can be switched between the clock signal CLK1 input to the second pin P2 and the clock signal input to the third pin, such a test apparatus supports both the DUTs shown in FIGS. 1A and 1B, which is convenient.